In the past, when signals are transmitted via a plurality of wirings, an external synchronous transmission scheme of separately transmitting data signals and clock signals or a self-synchronous transmission scheme of transmitting those signals without separating them. Particularly, in a case where a difference in a wiring delay between signal lines is increased, signals are often transmitted in accordance with the self-synchronous transmission scheme. In the self-synchronous transmission scheme, the receiving circuit detects a transition of a status of a reception signal, generates an internal clock signal to be inverted at a transition timing, and generates a data signal from a transition pattern thereof each time a status transitions. Here, the transition pattern indicates each set in a case where permutations in which a pre-transition status and a post-transition status are arranged in order are classified into two or more sets when a status transitions. For example, in a case where there are 6 statuses, the number of permutations in which a pre-transition status and a post-transition status are selected and arranged in order is 6×5 (=6P2), but in a case where they are classified into 5 sets, the number of patterns is 5. Further, a circuit subsequent to the receiving circuit acquires a data signal in synchronization with the internal clock signal.
Here, in the self-synchronous transmission scheme, the internal clock signal is inverted at a timing at which a value of the data signal changes. Therefore, if the subsequent circuit performs sampling on the data signal at an unstable timing at which the value of the data signal is changing, it is likely to fail to acquire the data signal. In this regard, a receiving circuit that generates a delay clock signal obtained by delaying an internal clock signal through a delay element and supplies the delay clock signal to a subsequent circuit together with a data signal has been proposed (for example, see Patent Document 1).